In the non-volatile semiconductor memory device disclosed in Japanese Unexamined Patent Publication No. 2001-176290 (Patent Document 1), as shown in FIG. 9, an initialization data region 130 of a memory cell array 110 is provided in a cell block, a minimum unit of data erase. The initialization data region 130 is predefined as a region to write initialization data for determining operating conditions of the memory.
A power-on reset circuit 270 detects power-on and, in response to detecting power-on, generates and provides a power-on detected signal to a control circuit 210. The control circuit 210 sets operation setoff the semiconductor memory device into a read-out mode a predetermined waiting time after power-on is detected to allow for stabilization of the power. Internal addresses are then sequentially incremented from an address register 220 and output to a row decoder 140 and a column decoder 170. Then, data in the initialization data region 130 is selected by the row decoder 140 and the column decoder 170, read out by a sense amplifier circuit 150, and transferred to and retained in a data register 160. The data is further transferred via a data bus to initialization data latch circuits 230 and 250 and a chip information data latch circuit 280 and retained therein.
The initialization data latch circuit 230 is configured with latch circuits LA1 to Lam, as shown in FIG. 10, where m is an integer related to the storage capabilities of the semiconductor memory device. The respective latch circuits LA are individually provided with a clocked inverter 410 for taking in a latch signal 420 and data. The initialization data latch circuit 250 and the chip information data latch circuit 280 are configured similarly.